Many memory devices, both volatile devices such as Random Access Memories (RAM) and nonvolatile devices such as Electrically Programmable Read-Only Memories (EPROM), include extra, i.e., redundant, memory cells that can be substituted for defective memory cells in the memory-cell array. Typically, such memory devices have their memory cells, both array and redundant, arranged in rows and columns. Because each memory cell is located at the intersection of a particular row and column, external circuitry addresses a memory cell by addressing both its row and column. The use of redundant memory cells often renders usable a memory device having one or more defective array memory cells, which otherwise would render the memory device unusable.
Typically, when a testing apparatus discovers a defective memory cell during initial testing of the memory-cell array, the testing apparatus configures a circuit within the memory device to map a column of redundant memory cells, i.e., a redundant column, to the address of the column containing the defective memory cell, i.e., the defective column. That is, when a cell within the defective column is addressed, the circuit enables the corresponding memory cell within the redundant column for data transfers intended for the defective cell. The same or another circuit typically disables the defective column to prohibit data transfers thereto or therefrom.
It is often desirable that the cells within a redundant column have access times at least as fast as the cells of the array columns. That is, it is desirable that the use of a redundant column incur no speed penalty for the memory device. It is also desirable that the memory device have good mapping flexibility. That is, it is desirable that the mapping circuit be able to map a particular redundant column to one of as many array columns as possible.
In some memory devices, however, the redundant columns are located such that the access times of their cells are significantly greater than the access times of the cells of the array columns. That is, because its access speed is slower, the use of a redundant column incurs a speed penalty for these memory devices. Thus, the specified access speed (i.e., the access speed specified on the device data sheet) of these devices often is reduced to accommodate the use of one or more redundant columns.
In other memory devices, the redundant columns are located such that the access times of their cells are approximately equal to the access times of the array cells. However, such location may increase the device's layout complexity, layout area, or number of components (such as transistors). Furthermore, such location may decrease the devices' mapping flexibility, i.e., may limit the number of redundant columns that can be mapped to a particular array column if it is defective.